SUMMARY

This PR introduces symbols for a few simple logic gates

• Schmitt triggers, inverting and non-inverting, without power pins

  • plain copy of the existing symbols, with the power pins removed
  • 
  • 

• 2-input AND, NAND, OR, NOR, XOR, XNOR gates

  • AND:
  • NAND:
  • OR:
  • NOR:
  • XOR:
  • XNOR:

Notes

• All gates are 4-squares high on the 2.54mm grid, like the original Schmitt triggers.
• The gates are named "Logic ", to appear grouped in the symbol list
• I am opening this PR since I'm working on a project using several 74-series ICs,
  • if the PR is accepted I'll follow up with separate PR to introduce multi-gate components, and devices in the manufacturer repo
• I know there is an existing PR ([Logic Gates] Add an AND gates IC #35 ) introducing the AND gate and associated devices; but I understand that with V2 the format of the symbols has changed

DATASHEETS / REFERENCES

None - symbols only in this PR

OPEN QUESTIONS / UNRESOLVED ISSUES

• the IN and OUT pin names in Schmitt triggers are not very readable.
  • However, this is the position they are in the current symbol; I didn't think necessary to change it
• I am not introducing a buffer and NOT symbols, as there are already symbols for "Buffer" and "Buffer Inverting"

CHECKLIST

• I have read and followed the library conventions¹.
• One note: one of the rules is "Use a pin length of 2.54mm if possible. Other pin lengths should be used only in special cases"
• the A and B pins on XOR and XNOR gates, and the Q pins on all N-gate are not 2,54mm long due to the additional elements, this is done to allow the extremity of the pin to sit on the 2.54mm grid
• Update: cursorily checking IEEE 91, the pins end on the inner ) - so they are 0.1in long
• For packages, I followed IPC7351C (see details in library conventions).
  • No packages are introduced
• For modified elements, I bumped their version number².
  • No elements are modified
• I already used the new library elements in a design and verified their correctness (optional).
  • Yes, but the project is at design stage
• I'm the copyright owner of the added content (i.e. the changes are made by myself, not copied/imported from somewhere else).
• I agree to publish all my changes under the CC0 Public Domain License³, allowing everyone to use and modify the content without any restrictions.

¹ Library Conventions: https://docs.librepcb.org/#libraryconventions
² Minor version bump if only metadata was modified (e.g. "0.1" -> "0.1.1"), major version bump if functional changes were made (e.g. "0.1" -> "0.2")
³ CC0 Public Domain License: https://en.wikipedia.org/wiki/CC0